Compiler Design 2

Outline s Refreshing Uncensored innovational . The Dr. Wangs original lecture s s s s s tutorial of pattern compiler s s entrance move Up the tutorial Graphical port wine The Alarm quantify bearing Setting digit Environment Setting conception Constraints Overview of optimization Phases Analysis of melodic theme DC tutorial 2 Introduction s s s Introduction s s s s The discount Process rule Compiler Products subtraction Programs and Tools plan Styles gossip and Output Formats User Interfaces hand file aways DC tutorial 4 The Synthesis ProcessStart Rewrite Verilog Code Read in protrude Set Attributes Set Realistic time Goal view as architectural plan Errors No Yes Fix Bugs Change Constraints Modify Compile Attributes Ungroup Design Blocks The DC Products s DC Professional No multi-frequency clocking, latch-based time borrowing, pipeline re-timing, exact path resynthesis, in-place optimization, and incremental editing s DC Expert involve features for maximi zing performance s FPGA Compiler Targets only FPGA technology optimize No Good? Yes D hotshot DC Tutorial 5 DC Tutorial 6 1 Synthesis Tools HDL Design analyser HDL Compilers DesignW are DesignWare DeveloperArchitectural optimization s s Architectural optimization Gate-Level s s Design Analyzer Logic optimization Design Compilers Cell program subroutine library Library Compiler s s arithmetic Optimization quantify and Area-Based Re credit Sharing Sub-expression Removal Constraint-Driven Resource infusion Inference of Synthetic Part (DesignWare) For more in pution HDL Compiler for Verilog Reference Manual Optimized Gate-level Netlist DC Tutorial 7 DC Tutorial 8 DesignWare s DesignWare Developer Provide a library of high-level purpose components bring iners, Multiplier, etc. s sThe HDL compiler will look at the proper components for you based on your timing and area goals See b call for and butter Collection (open collection) Synopsys DesignWare 1997. 01 s Create Design Ware Libraries DC Tutorial 9 DC Tutorial 10 DC Products s Cell Library s Library of basic kiosks used by DC AND, OR, XOR, etc. s Optimize your role at the gate level Using opted electric cell libraries s For FPGA compiler, it may contain more complex cells Xilinx CLBs, IOBs, etc. DC Tutorial 11 DC Tutorial 12 2 Library Compiler Design Styles s Yes, you can create your own cell libraries s s Hierarchical or Flatten Combinational or SequentialDC Tutorial 13 DC Tutorial 14 Input Formats s s s s Output Formats s s s s s VHDL Verilog PLA & EDIF 2. 00 Xilinx XNF s Synopsys binary format (. db records) VHDL Verilog EDIF 2. 00 Equation, LSI Logic, Mentor Graphics, PLA, resign table, Tegas formats Xilinx XNF format DC Tutorial 15 DC Tutorial 16 User Interfaces s Scripts s shell dc_shell unix-like ascendency shell dc_shell quit dc_shell cd my_dir dc_shell alias wv write -f verilog dc_shell pwd dc_shell history n dc_shell list - demand dc_shell man dc_shell sh lpr s s s s shell design_analyzer in writing(p) interface DC Tutorial 17 A personate of command can be put together into a file called hired man Then, you dont need to re-type some the commands again and again when apply the dc_shell Scripts for this tutorial will be provided for your reference You can run them when you are home without the X-windowpane capability DC Tutorial 18 3 rate Documentation s s s s s s s shell design_analyzer & select Help On-Line Documentation . Ignore the second power window with Titles select Cancel to close it focus on the one with File, Edit, View select File Open Collection select Synopsys Synthesis Tools 1997. 1 and hence click OK select Documents Formatted for Printing and then click Open In the File, Edit, View window, now you can select a list of on-line documents DC Tutorial 19 Setting Up the Tutorial Setting Up the Tutorial s s s s Creating The Directories s cp -r /baby/synopsys/doc/syn/tutorial . al-Qaida Directory tutorial Creating t he directories Setting paths and aliases Creating a start-up file take onning tutorial with scripts db/ verilog/ vhdl/ appendix_A/ Script files work (empty) DC Tutorial 21 DC Tutorial 22 Path s s .synopsys_dc. setup file % source /usr/local/bin/setup. synopsys Or you can put it in . cshrc file % source . cshrc % rehash s s You can take a look of the setup file % more /usr/local/bin/setup. synopsys s Creating a . synopsys_dc. setup file can overwrite system disregard settings % cp /tutorial/. sysnopsys_dc. setup /. synopsys_dc. setup % vi /. synopsys_dc. setup company = Motorola somerset designer = CEO view_background = epoch s It basically setup the reform environmental variables for you DC Tutorial 23 DC Tutorial 24 4More about setup file s Scripts s s % more . synopsys_dc. setup search_path = + search_path link_library target_library symbol_library define_design_lib s s s s s search_path = a directory + search_path if you cp tutorial into a directory other than home link_library locating of subdesgins referenced by the design target_library identify technology libraries symbol_library identify symbols library for generating/viewing schematics define_design_lib identify a temporary place to store middling files created by the analyzer DC Tutorial 25 No X-Window, No Problem Find script files in /tutorial/appendix_A/. See Design Analyzer Reference Manual for more detail DC Tutorial 26 Graphical Interface s s Start % design_analyzer & cast off claim File Quit Menu Bar Graphical Interface View acquittances Level Buttons Scroll Bar Message Area (view_background = while) View Window DC Tutorial 28 Mouse Buttons s Check Default Setup s Setup Defaults Left Button Select design and design objects s Mid Button Add or remove objects from a group of objects al exhibity selected s sound Button Bring up the pop-up add-in DC Tutorial 29 DC Tutorial 30 5 Read in a Design s notwithstanding a Design s File analyze & elaborate repr esent File Save or Save As Once a design is selected s analyze read in VHDL/Verilog check for syntax and synthesizale logic store as intermediate formats Use to read each sub-design + top level design s elaborate create the design from intermediate formats determine the correct carriage size Use for top level design + sub-design with parameters passing in s read read design formats other than HDL (db, PLA, tc. ) DC Tutorial 31 DC Tutorial 32 A Design Has 4 Views s s s s s Design View s Design View Symbol View schematic drawing View Hierarchy View T View (No Use) After read in all 13 verilog files in the tutorial directory you first show the Design View DC Tutorial 33 DC Tutorial 34 Symbol View s Schematic View s Select TIME_STATE_MACHINE and double-click on it - you enter the symbol view of the design flicker on the schematic view button on the left run side DC Tutorial 35 DC Tutorial 36 6 Hierarchy View s Design View Icons s s s sClick the up arrow (left passel side) to go back to design view doubleclick on TOP Select View Change View Hierarchy TOP contains 6 modules Netlist read in as a netlist and optimized to gates Equation In VHDL, Verilog, or equation format that is partially or completely behavioral PLA contract in PLA format State set back Specified in state table format Y=A+B 010-0 1-101 PLA State Table Netlist Equation DC Tutorial 37 DC Tutorial 38 Command Window s dc_shell Commands Setup Command Window s For more information, see Design Compiler Reference Manual fundamental principle DC Tutorial 39DC Tutorial 40 Design Attributes s Operating Environment Sub-menu s Attributes are values you set to control the optimization process Select Attributes from the menu s The Attributes menu provide access to Set input and output delays Set shoot for strengths set loads Characterize subdesigns Select operating conditions Choose a wire load model Create or modify a clock DC Tutorial 41 Set design properties that desc ribes the sexual conditions of a design and the designs interaction with its surrounding shoot for strength on ports the time that signals arrive on ports load control by output portsDC Tutorial 42 7 Optimization Constraints s Design Optimization s Set the goal for design optimization largest delay allowed greatest area allowed Select Tools Design Optimization See Design Compiler Reference Manual Optimization and Timing Analysis for more detail s Two set-constraint windows Design Constraints window Goals for area and power Design rules implied by technology library Test-related constraints (testability) Timing Constraints window Timing constraints s DC Tutorial 43 DC Tutorial 44Locating Problems s Generate Report s Before and after optimization, use Schematic View and Check Design to locate problems Generate schematic view Select Analysis Check Design Jump to a design object Click on an wrongful conduct or warning message in the Design error window Click on the show button Analysis Report DC Tutorial 45 DC Tutorial 46 Run a Script File s Setup Execute Script check out /tutorial/appendix_A/*. script dc_shell include The Alarm quantify Design DC Tutorial 47 8